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Hacking your own FPGA chip scope

Ok, why would we want to do that, when there are various existing solutions:

  • Altera SignalTap
  • Xilinx ChipScope
  • Lattice Reveal

Make a long story short: To be in control! Well, there were some quirks with existing code, some tools wouldn’t run on my OS, and I wanted to be vendor independent.

But one major reason: We wanted to debug our own DSP core based system while eavesdropping on some internal signals.

So there we go with the shopping list:

  1. JTAG port and TAP implementation [already done]
  2. JTAG agent for debugging and BSCAN register monitoring [already done]
  3. Output to ‘live’ wave display

So again, a little hack of a VCD output got me going. Basically, a specific JTAG register is continously polled in the main loop and the output is written to a VCD file. Like we did it here (JTAG debugging movies), this is now taken on to real hardware.

You basically need a netpp installation for the header and the source files below:

scope.c : The VCD output for a homemade scope

scope.h : Necessary header

So what you do to build your own scope (that works with any other data source, by the way): Write the VCD data to a file, and meanwhile you run GTKwave under Linux as follows:

shmidcat /tmp/out.vcd | gtkwave -v -I run.sav

When selecting View->Partial VCD dynamic Zoom End within GTKwave, the window will scroll along your output. There are some compression options for GTKwave when the data file is getting too big.

Note also: GTKwave will overflow after a while. So make sure the time unit somewhat matches your resolution.

Ok, and now you might note that there is some draw back to this: The resolution might be pretty bad, the scope just shows a current state read out at some rather fuzzy defined real time. Some glitches or fast changes are not recorded!

So this needs a more advanced version which I won’t cover here, as it is highly specific to the problem you’re debugging. Just as a guide line: You’ll have to set up an internal trace buffer in block ram that will monitor the interesting signals and record every change in some way. Then you read out this trace buffer through another channel (which does not have to be JTAG in particular). This technique gets way closer to what the more professional tools are doing: triggering a trace on a specific event and recording them to memory, possibly in a compressed way. And there you go: You’ll be able to write your own logic analyzer and find out that the pro tools not always would save you the time.

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