SoC Overview

All SoC designs include the following peripherals by default:

Base: GPIO(2), SPI(1), TIMER(3), PWM(3), UART(1)

If multiple instances are possible, the maximum number of units configured for this SoC are listed in brackets.

SoC ID CPU/Arch SCACHE IRQ Peripherals DMA Reference platform License Applications
agathe Zealot/ZPU n 1 PWM(8) 0 (1) OS Configuration µP
agneta ZPUng v1 y 4 EFB MACHXO hard IPcore 0 (1) C Multi I/O PWM control
bertram ZPUng v1 y 4 PWMPLUS 0 (2) C Multi LED strip controller
dombert ZPUng v1.1 n 4 CPK, JPEG, MAC,  DMAA 2 (3), (4), (5)  CS MJPEG encoding/streaming SoC
dagobert ZPUng v1.1 y 6 MAC, PWM(3), DMAA 2 netpp node C netpp/UDP SoC (Analog I/O)
emil ZPUng v2

RISC-V 32ui

y 6 MAC, DMAH, GDP, FLiX 4 (custom) CS High speed signal/data processing SoC, dual core capable

License codes:

OS: OpenSource, C: Source available under Custom agreement, CS: Closed Source, N/A: under development

Third party reference platforms

  1. Mach XO2/XO3 breakout board [Link]
  2. Papilio Spartan3 250k [Link]
  3. Lattice HDR60 camera eval platform [Link]
  4. Lattice Versa ECP5G eval board [Link]
  5. Lattice EVDK (VIP) video processing eval board [Link]
  6. Trenz TE0600 based custom eval board [Link]

Development kit

Peripheral IP Cores:

  • SCACHE: Virtual ROM (SPI cache). Enhances program memory up to several MB of ROM code for program overlay or data storage
  • DMA/DMAA: Simple DMA/Autobuffer DMA engine for high speed transfers with little CPU interference
  • LCDIO: Custom LCD driver engine
  • SPI: 32 bit word capable SPI I/O, DMA capable on d* SoCs.
  • TWI: proprietary i2c peripheral (with clock stretching)
  • PWMPLUS: Improved PWM for realtime pulse width control
  • FX2FIFO: Cypress FX2 FIFO interface for fast isochronous data transfer
  • GDP: Generic data port (Video or any other framed data)
  • MAC: Ethernet MAC interface for RGMII or GMII capable Phy Circuits
  • CPK: Proprietary image processing pipeline ‘COTTONPICKEN’
  • SPORT: Fast serial port for audio codec I/O, DMA capable
  • JPEG: JPEG hardware encoder
  • FLiX: proprietary microcode engine for DSP applications (ZPUng v2 only)

Reference SoC details


  • Zealot (Opensource) CPU
  • FPGA Family supply for MACHXO2, Spartan3, Spartan6

License: OpenSource for eval

Reference applications:
  • Simple but slow (minimum 4 clock cycles per operation) configuration processor for i2c devices
  • Protocol translator from multiple i2c sensors to UART
  • PWM controller

agneta, beatrix/bertram

  • ZPUng (proprietary section5) CPU, pipelined, 1 cycle per op
  • Supports: MACHXO2, MACHXO3 (a* families), Spartan3, Spartan6, ECP3 (a* and b* family)

License: Proprietary non-OpenSource, Sourcecode licenseable

Reference applications
  • Safety relevant IoT applications (netpp on FPGA)
  • Multi channel WS2812B LED strip control through PWMPlus IP core
  • TFT/LCD display interfacing


The dombert SoC is a SoC optimized for MJPEG streaming (90 kHz time base RTP, RFC2435) and video processing applications.


  • Software-defined Ethernet stack for up to 50 MB/s throughput (Gigabit Ethernet).
  • Autobuffer DMA scatter/gather engine for high throughput streaming from a generic data port
  • Vendor invariant implementation of low latency controllable packet FIFOs
  • FPGA debugging support for Xilinx Spartan6, Kintex7, Lattice ECP3, ECP5
  • Sensor control (i2c interface) for parameter switching during image blanks
  • ‘dombert’ brief/MJPEG streaming demo [ english ]


The dagobert SoC is a specific edition for the netpp_node development kit and is a dombert derivative with high speed streaming options for real time systems.

  • High speed UDP Ethernet network stack
  • DMAA scatter/gather engine for data port transfers without CPU intervention
  • 32 I/O pins with pin multiplexing options
  • SPI data/program cache for user storage

Reference applications: netpp IoT stack with UDP/IP, ARP and ICMP support



The emil SoC is a high speed optimized, experimental ZPUv2 core that runs at higher clock speed and uses extended microcode features to allow inline digital signal processing routines. It can run as dual core with shared L2 RAM on bigger FPGAs.

Update: riscv32ui(c) support under scrutiny. This configuration allows to swap out the CPU core without modification of the main program source.


  • High speed UDP Ethernet network stack, Gigabit MAC
  • DMAH high speed engine for data routing between MAC, CPU, GDP and coprocessor
  • FLiX DSP coprocessor with inline emulation

Documentation is not yet frozen. Work in progress…

Legacy SoC designs

These SoC designs are frozen and no longer maintained. Only listed for reference.


No longer maintained, all new developments is merged into bertram.

beatrix is now considered ‘opensource playground’ and included in the MaSoCist public/opensource distribution.


No longer maintained. All ‘cordula’ development is merged into the new ‘dombert’ SoC configuration.


The dorothea SoC (based on the legacy PyPS core) is superseded by the dombert SoC using the ZPUng v1.1 architecture. It is meant to be the full drop-in replacement for the dorothea MJPEG/h264 accelerator and streaming engine.