For quite a while I wouldn’t have said, it’s impossible, but wouldn’t put much effort in it either. Why, if you have a spare $1 microprocessor that can run a simple netpp communication stack just fine.
Well, sometimes it’s time to try something else: Running a soft core CPU (ZPU) on small FPGAs has found some interest, due to the limited resource consumption, but full freedom when it comes to specific interfaces, such as
- Programmable PWM engines (motor control)
- Many RS485 capable interfaces (that classic uCs don’t have)
- Safety proof specific state machines
The ZPU will even fit on a $5 FPGA and still leave enough space for the specific interfaces. It is a slow stack machine, even the fastest pipelined implementations don’t really beat the MIPS alike architectures, however this doesn’t bother us when we just have to configure a set of registers, moreover, the ZPU architecture compensates with quite some code density.
This solution was presented on the Embedded World Conference 2016 in Nuremberg. The published documentation can be downloaded for free in the web shop.
[ Update 01/2018 ]
After many proof of concepts and field tests, an eval kit for some real networked FPGA fun is out: the netpp node, featured by a high speed UDP engine. Earlier solutions were using a Wiznet chip, the WLAN hack using the horrible esp8266 chipset turned out to be unusable for industrial purposes. The current two chip (FPGA and Phy) solution works so far most robust.