Find the a (currently unstable) development branch here:
Configurations that work (from those appearing when you run ‘make which’ in the masocist top dir):
- *-zpu-ghdlsynth: ZPUng setup with ‘beatrix’ configuration.
- *-pyrv32-ghdlsynth: RISC-V 32 bit basic configuration, proof of concept only, not fully functional as SoC in synthesis (as of now)
Note: You need to explicitely install the rv32 toolchain (inside the docker container) for this config:
sudo apt-get install riscv32-binutils riscv32-gcc riscv32-newlib-libc
This can be done online in a browser, if you don’t run Linux, see also https://section5.ch/index.php/2019/10/24/risc-v-in-the-loop/.
Note: Since this setup depends on external packages, there is no guarantee it will build smoothly.
- Run docker container with exported USB devices (if you want to program the plugged in board right away):
docker run -it --device=/dev/bus/usb hackfin/masocist:synth
- Pull synthesis self-extracting build script:
wget https://section5.ch/downloads/masocist-synth_sfx.sh && sh masocist-synth_sfx.sh
- Pull packages and build:
- Configure platform:
- Build for synthesis:
make clean sw syn
- When successful, you’ll end up with a $(PLATFORM).SVF file in
- See next paragraph on how to program the board (this procedure will be simplified)
Currently, the following ECP5 based boards are supported/under scrutiny:
- Lattice Versa development kit [Lattice Semiconductor product page]
- Testing: EVDK/VIP stereo sensor development kit [Lattice Semiconductor product page]
Programming with on board FT2232H JTAG interface:
Note that programming will only work when the container is run/started after plugging in the board.
To program the FPGA SRAM on the board with the produced SVF file:
- Make sure board is connected via USB and powered up.
- You may need to restart the container from above:
docker start -i <id>
where ‘id’ is the container id of the above stopped container (retrieve from shell history or with
docker ps -a)
- Install openocd:
sudo apt-get install openocd
- Make sure board is connected via USB and powered up, then run, inside $(MASOCIST)/syn:
make download OPENOCD="sudo openocd"
- If you see a lot scrolling by, board programming tends to be successful (interface was recognized). You can ignore errors like:
Error: tdo check error at line 26780
as they are due to the changed USERCODE.
- You should see the segment display on the board ‘spinning’. Also, you can talk to the SoC through the UART at 115200, 8N1, for example using minicom:
minicom -o -D /dev/ttyUSB1
The output upon booting of the SoC should be:
Probing flash… Flash Type: m25p128 Booting beatrix HW rev: 04 @25 MHZ ------------- test shell ------------- -- SoC for Versa ECP5 -- arch: ZPUng -- (c) 2012-2020 www.section5.ch -- -- type 'h' for help --
Short summary on what works in particular and what does not:
RAM inference is currently problematic and needs to be investigated further. TODO:
- Make synthesis recognize more variants of RAM with init values
- Implement dual process true dual port RAM
- Fully eliminate Verilog RAM wrapper workarounds
Some FSM seem to optimize away in yosys. Needs to be investigated if it’s a VHDL synthesis or internal Yosys issue.
Vendor specific Black Box primitives currently need to be wrapped explicitely via Verilog, see also:
You’ll find an example in this repo in
examples/ecp5_versa. See also
library/wrappers on how to integrate black boxes. An
ecp5um.components package was added to the above library.
So far tested primitives within MaSoCist:
- JTAGG: Test access port to ZPUng and pyrv32 for JTAG debugging or automated in circuit emulation hardware tests.
- EHXPLLL: PLL primitive for clock frequency conversion
- USRMCLK: Access to SPI master clock on ECP5
System Interrupt Controller (CONFIG_SIC) is currently not supported: #1140
Fixed. Make sure to install the up to date debian GHDL packages when reusing an old container:
sudo apt-get update; sudo apt-get install ghdl ghdl-libs
You also have to rebuild the ghdl.so module in src/ghdlsynth-beta:
make clean all; sudo make install
- FLiX DSP and JPEG core unsupported (due to true dual port RAM issues)
- Under scrutiny: pktfifo (CONFIG_MAC) problematic (TDP BRAM issues)
- Post map simulation does not work with DP16KD primitives, due to missing ‘whitebox’ model, see also #32. You will have to separately use the supplied vendor model from the Diamond libraries.