There are various approaches to Python HDLs, some more suited to Python developers than to HDL developers. They all have one thing in common: The very refined test bench capabilities of the Python ecosystem which allow you to just connect almost everything to all. From all these Python dialects, myHDL turns out to be the most readable and sustainable language for hardware development. Let me outline a few more properties:
- Has a built-in simulator (limited to defined values)
- Converts a design into flattened Verilog or VHDL
- Uses a sophisticated ‘wire’ concept for integer arithmetics
In a previous post, I mentioned experiments with yosys and its Python API. Not much has changed on that front, as the myHDL ‘kernel’ based approach turned out to be unmaintainable for various reasons. Plus, the myHDL kernel has a basic limitation due to its AST-Translation into target HDLs that impedes code reusability and easy extendability with custom signal types.
For experiments with higher level synthesis, such as automated pipeline unrolling or matrix multiplications, a different approach was taken. This ‘kernel’, if you will, can handle the legacy myHDL data types plus derived extensions. This works as follows:
- Front end language (myHDL) is slightly AST-translated into a different internal representation language (‘myIRL’)
- The myIRL representation is executed within a target context to generate logic as:
- VHDL (synthesizeable)
- RTL (via pyosys target)
- mangled Verilog (via yosys)
Now the big omnipresent question is: Does that logic perform right? How to verify?
- The VHDL output (hierarchical modules) is imported into the GHDL simulator and can be driven by a test bench. The test bench is also generated as a VHDL module. Co-Simulation support is currently not provided.
- The Verilog output can be simulated with iverilog, however, Co-Simulation is not enabled for the time being for this target
- The RTL representation is translated to C++ via the CXXRTL back end and is co-simulated against the Python test bench. Note that support for signal events are rudimentary. CXXRTL is targeting at speedy execution with defined values (no ‘X’ and ‘U’)
Instead using classic documentation frameworks, the strategy was chosen again to use Jupyter Notebooks running in a Jupyter Lab environment. Again, the Binder technology enables us to run this in the cloud without requirement to install a specific Linux environment. The advantages:
- Auto-Testing functionality for notebooks in a reference Docker environment
- Reduced overhead for creating minimum working examples or error cases
This Binder is launched via the button below.
Overview of functionality:
- Generation of hardware as RTL or VHDL
- Simulation (GHDL, rudimentary CXXRTL)
- RTL display, output of waveforms
- Application examples:
- Generators (CRC, Gray-Counter, …)
- Pipeline and vector operations
- Extension types (SoC register map generation, etc.)
Yosys synthesis and target architectures
The OpenSource yosys tool finally allows to drop a reference tool chain flow into the cloud without licensing issues. This is in particular interesting for new, sustainable FPGA architectures. A few architectures have been under scrutiny for ‘dry dock’ synthesis without actually having hardware.
In particular, a reference SoC environment (MaSoCist) was dropped into the make flow for various target architectures to see:
- How much logic is used
- If synthesis translates into the correct primitives
- If the entire mapped output simulates correctly with different simulators
The latter is a huge task that could only be somewhat automated using Python. Therefore, the entire MaSoCist SoC builder will slowly migrate towards a Python based architecture.
It is expected to document some more in particular about several architectures.
As an example, a synthesis and mapping step for a multiplier:
Limitations
As always with educational software, some scenarios don’t play. The restrictions in place for this release:
- Variable usage in HDL not supported
- Custom generators, such as Partial assignments (
p(1 downto 0) <= s) or vector operations not supported in RTLIL - Limited support for
@blockinterfaces - Thus: No HLS alike library support through direct synthesis (yet)
Exploring CXXRTL
CXXRTL by @whitequark is a relatively fresh simulator backend for yosys, creating heavily template-decorated C++ code compiling into a binary executable simulation model. It was found to perform quite well as a cythonized (compiled Python) back end driven from a thin simulator API integrated into the MyIRL library.
Since it requires its own driver from the top, a thin simulator API built on top of the myIRL library takes care of the event scheduling, unlike GHDL or icarus verilog which handle delays and delta cycling for complex combinatorial units. It is therefore still regarded as a ‘know thy innards’ tool. A few more benefits:
- Allows to distribute functional simulation models as executables, without requirements to publish the source
- Permits model-in-the-loop scenarios to integrate external simulators as black boxes
- Eventually aids in mixed language (VHDL, Verilog, RTL) and many-level model simulations
There are also drawbacks: Like the MyHDL simulator, CXXRTL is not aware of ‘U’ (uninitialized) and ‘X’ (undefined) values, it knows 0 and 1 signals only. It is therefore not suitable for a full trace of your ASIC’s reset circuitry without workarounds. Plus, CXXRTL only processes synthesizeable code and would not provide the necessary delay handling for post place and route simulation.
Co-Simulation: How does this play with MyHDL syntax?
This is where it gets complicated. MyHDL allows a a subset of Python code to be translated to Verilog of VHDL such that you can write simple test benches for verification that run entirely in the target language.
Then there’s the co-simulation option, where native Python code (featured by the myHDL ‘simulator kernel’, if you will) runs alongside a compiled simulation model of your hardware. The simplest setup is basically a circuit or entire virtual board with only a virtual reset and clock stimulus. Any other simulation model, like as UART, a SPI flash, etc. can be connected to such a simulation with more or less effort. The big issue: Who is producing the event, who is consuming it? This leads us back to the infamous master and slave topic (I am aware it’s got a connotation).
The de-facto standards aiding us so far in the simulator interfacing ecosystem:
- VHDL: VHPI, VHDLDIRECT, specific GHDL implementations
- Verilog/mixed: VPI, FLI
- QEMU as CPU emulation coupled to hardware models
The easiest to handle may be the VPI transaction layer, that is already present for myHDL. In this implementation, it is using a pipe to send signal events to the simulation and reading back results through another reverse path. Here, the myHDL plays a clear master role. For GHDL, a asynchronous concept was explored via my ghdlex library, allowing distributed co-simulation across networks where master and slave relationships are becoming fuzzy.
Finally, the CXXRTL method provides most flexibility, as we can add blackbox hardware that does just something. We have the full control here over a simple C++-layer without any overhead induced through pipes. The binding for Python can easily be created using Cython code. However it requires to clearly separate testbench code from hardware implementation.
This implies:
- Test bench must be written in myHDL syntax style and needs to use specific simulation signal classes
- Extended bulk signal/container classes re-usage is restricted
- Hardware description can be in any syntax or intermediate representation, as well as blackbox Verilog or VHDL modules
Links and further documentation
As usual in the quickly moving opensource world, documentation is sparse and solutions on top of it are prone to become orphanware, once the one man bands retire or lose interest. However, I tend to rate the risk very low in this case. Useful links so far (hopefully, there’ll be found more soon):
Disclaimers
- Recommended for academical or private/experimental use only
- The pyosys API (Python wrapper for libyosys) may at this moment crash without warning or yield misleading feedback. There’s not much being done about this now as updates from the yosys development are expected.
- Therefore, jupyter notebooks may crash and you may lose your input/data
- No liability taken!