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RISC-V in the loop

Continuous integration (‘CI’) for hardware is a logical step to take: Why not do for hardware, what works fine for software?

To keep things short: I’ve decided to stick my proprietary RISC-V approach ‘pyrv32’ into the opensourced MaSoCist testing loop to always have an online reference that can run anywhere without massive software installation dances.

Because there’s still quite a part of the toolchain missing from the OpenSource repo (work in progress), only a stripped down VHDL edition of the pyrv32 is available for testing and playing around.

This is what it currently does, when running ‘make all test’ in the provided Docker environment:

  • Build some tools necessary to build the virtual hardware
  • Compile source code, create a ROM file from it as VHDL
  • Build a virtual System on Chip based on the pyrv32 core
  • Downloads the ‘official’ riscv-tests suite onto the virtual target and runs the tests
  • Optionally, you can also talk to the system via a virtual (UART) console

Instructions

This is the quickest ‘online’ way without installing software. You might need to register yourself a docker account beforehand.

  1. Log in at the docker playground: https://labs.play-with-docker.com
  2. Add a new instance of a virtual machine via the left panel
  3. Run the docker container:
    docker run -it hackfin/masocist
  4. Run the test suite:
    wget section5.ch/downloads/masocist_sfx.sh && sh masocist_sfx.sh && make all test
  5. Likewise, you can run the virtual console demo:
    make clean run-pyrv32
  6. Wait for Boot message and # prompt to appear, then type h for help.
  7. Dump virtual SPI flash:
    s 0 1
  8. Exit minicom terminal by Ctrl-A, then q.

What’s in the box?

  • ghdl, ghdlex: Turns a set of VHDL sources into a simulation executable that exposes signals to the network (The engine for the virtual chip).
  • masocist: A build system for a System on Chip:
    • GNU Make, Linux kconfig
    • Plenty of XML hardware definitions based on netpp.
    • IP core library and plenty of ugly preprocessor hacks
    • Cross compiler packages for ZPU, riscv32 and msp430 architectures
  • gensoc: SoC generator alias IP-XACT’s mean little brother (from another mother…)
  • In-House CPU cores with In Circuit Emulation features (Debug TAPs over JTAG, etc.):
    • ZPUng: pipelined ZPU architecture with optimum code density
    • pyrv32: a rv32ui compatible RISC-V core
  • Third party opensource cores, not fully verified (but running a simple I/O test):
    • neo430: a msp430 compatible architecture in VHDL
    • potato: a RISC-V compatible CPU design

IP cores

Overview:

The MaSoCist build system

Pun intended: Applying a linux kernel configuration approach onto a hardware system turned out to be painful. However, it pays off:

  • Cross platform: Simulate and synthesize reusable code for various architectures (Lattice, Xilinx, Altera FPGAs)
  • Configure peripheral interface instances like a linux kernel
  • Automated generation of address decoders, peripheral instances and memory map from gensoc – our in house SoC generator.
  • Generate hardware configuration, software drivers and corresponding register documentation in one call: ‘make all’
  • Continuous integration for hardware designs: Run test benches automatically in the cloud for hardware verification

It allows vendor specific designs and extensions without the need to OpenSource, therefore it is available in two license variants:

A fully usable Docker container is hosted at: https://hub.docker.com/r/hackfin/masocist/, use

docker pull hackfin/masocist

to download this container. If you want to run this on a Windows client, see Windows setup notes.

MaSoCist opensource primer: [sdm_download id=”1412″ fancy=”0″]

IP blocks and cores

Cottonpicken Engine

The Cottonpicken Engine is an in-house micro coded digital signal processing (DSP) engine that has the following functionality:

  • Bayer pattern decoding into various formats (YUV 4:2:2, YUV 4:2:0, RGB, programmable delays)
  • YUV conversion supports YCrCb, YCoCg as well
  • 3×3, 5×5 filter kernels
  • Specific matrix operations, cascadeable

It is capable of running at full data clock (pixel clock) up to 150 MHz (platform dependent).

The engine is only available as a closed source netlist object as part of a development package.

Image compression

JPEG Encoder IP

Our in-house designed, machine vision proof JPEG encoder and streaming solutions available for usage in standard FPGAs at low costs (at typically below 35’000 EUR support costs per project). The supported pixel bit depth is up to 12 bits. The JPEG IP is available in two standalone variants:

  • L1 monochrome multiplexed pipeline (150 MHz pixel clock on Spartan6)
  • L2 dual pipe simultaneous encoding for high quality YUV422, for example 1280×720@60fps (up to 100 MHz pixel clock)
  • L2H: Higher pixel clock variant (up to 200MHz) available for specific platforms

Fully deployable UDP/Ethernet (RFC 2435) streaming solutions and camera reference designs are available as well. The receiver’s software side is covered with embedded gstreamer OpenSource appplications that run on Linux and Windows platforms, likewise.

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Lossless and other compression methods

We have extensive know how on:

  • High speed DPCM-Compression (up to 200 MHz pixel clock, 16 bit, lossless, suitable for medical images, full simulation model available). Can be made software-compatible to lossless JPEG (not JPEG-LS).
  • Multirate adaptive predictors for special imagery (lossy coding / quantization support)
  • Wavelet coding kernels (lossy and lossless)
  • Combined, lossy approaches, non-standard (partial JPEG2000 transcoding possible)
  • Huffman/Golomb-Rice coding IP core, dual-channel (simultaneous throughput of Luma/Chroma channels).

cCAP SoC Reference designs

These System on Chip designs consist of a fully configureable CPU plus standard peripherals and can be customized with special interfaces. The CPU can be programmed with GCC and is accessed via ICE JTAG during development. The underlying build and configuration system and some of the peripherals are available as Open Source, see MaSoCist.

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Simulation models

Full simulation models are available for all our IP cores that can be co-simulated with custom IP or run ‘live’:

See also VirtualChip page.

Hardware-Design

section5 besitzt eine reichhaltige Erfahrung in den Bereichen Elektronik und Signalverarbeitung auf verschiedenen Plattformen, von einfachen diskreten Mikrocontroller-Entwicklungen über komplexe Linux-Systeme bis hin zur Simulation und Implementierung von FPGA Designs (MyHDL/VHDL):

  • Embedded Linux, bare metal crt0.s, GNU, Kerneltreiber
  • FPGA-Programmierung, GPU/DSP cores
  • CAD 3D und Visualisierung
  • Prototypenbau, Referenzdesigns

Beispielanwendungen:

CAD und Prototypen

Rendering FPGA-Platine

Beispielplatine ‘denverII’

Schnell am Markt mit einem funktionierenden Prototypen – aus einer Hand:

  • PCB-Design-Tools (Kicad, Eagle, Altium möglich)
  • 3D CAD und Visualisierung (Photo-Rendering-Studien)
  • Neu: faltbare Gehäuseprototypen (Papier, Plastik, Metall)
  • manuelle PCB-Bestückung, Unterstützung für Fertigung von Kleinserien mit gängigen Bestückern
  • Testbench für Massenfertigung von Erstserien

FPGA IP Cores und CPU-Designs

>> Kundenspezifische Prozessorlösungen

Tools

Unsere ‘in-house’-Tools sind teilweise OpenSource oder im Rahmen von Entwicklungspaketen verfügbar:

  • ghdlex: Co-Simulation von Soft/Hardware
  • gensoc: SoC-Peripherie-Generator (CPU-Definition netpp -> HDL), IP-XACT/Qsys Translation
  • Build-System für SoCs auf unterschiedlichen FPGA-Plattformen