SoC Overview

All SoC designs include the following peripherals by default:

Base: GPIO(2), SPI(1), TIMER(3), PWM(3), UART(1)

If multiple instances are possible, the maximum number of units configured for this SoC are listed in brackets.

SoC ID CPU/Arch SCACHE IRQ Peripherals DMA Reference platform License Applications
agathe Zealot/ZPU n 1 PWM(8) 0 (1) OS Configuration µP
beatrix ZPUng v0/v1 y 4 LCDIO 0 (2) C Configuration µP with LCD
agneta ZPUng v1 y 4 EFB MACHXO hardened IP 0 (1) C Multi I/O PWM control
bertram ZPUng v1 y 4 PWMPLUS 0 (2) C Multi LED strip controller
cordula ZPUng v1 n 4 I2C, JPEG, VIDEO in/out (DVI) 2 (3) C  JPEG Encoder SoC
cranach ZPUng v1.1 n 4 Base, PWMPLUS(3), UART, MAC, DMA 2 (4),(5) C netpp processor
dombert ZPUng v1.1 n 2 CPK, JPEG, MAC, DMAA 2 (3), (4), (5)  CS MJPEG streaming SoC

License codes:

OS: OpenSource, C: Source available under Custom agreement, CS: Closed Source, N/A: under development

Peripheral IP Cores:

  • SCACHE: Virtual ROM (SPI cache). Enhances program memory up to several MB of ROM code for program overlay or data storage
  • DMA/DMAA: Simple DMA/Autobuffer DMA engine for high speed transfers with little CPU interference
  • LCDIO: Custom LCD driver engine
  • SPI: 32 bit word capable SPI I/O, DMA capable on d* SoCs.
  • TWI: proprietary i2c peripheral (with clock stretching)
  • PWMPLUS: Improved PWM for realtime pulse width control
  • FX2FIFO: Cypress FX2 FIFO interface for fast isochronous data transfer
  • MAC: Ethernet MAC interface for RGMII or GMII capable GigE Phy
  • CPK: Proprietary image processing pipeline ‘COTTONPICKEN’
  • SPORT: Fast serial port for audio codec I/O, DMA capable
  • JPEG: JPEG hardware encoder
  • FLiX: proprietary microcode engine for DSP applications (ZPUng v2 only)

Reference platforms

  1. Mach XO2/XO3 breakout board [Link]
  2. Papilio Spartan3 250k [Link]
  3. Lattice HDR60 camera eval platform [Link]
  4. Lattice Versa ECP5G eval board [Link]
  5. Trenz TE0600 based custom eval board [Link]

Reference SoC details

 

agathe/anselm

  • Zealot (Opensource) CPU
  • Family supply for MACHXO2, Spartan3, Spartan6

License: OpenSource for eval

Reference applications:
  • Simple but slow (minimum 4 clock cycles per operation) configuration processor for i2c devices
  • Protocol translator from multiple i2c sensors to UART
  • PWM controller
Short reference documentation

 

agneta, beatrix/bertram

  • ZPUng (proprietary section5) CPU, pipelined, 1 cycle per op
  • Family support for MACHXO2, MACHXO3 (a* families), Spartan3, Spartan6, ECP3 (a* and b* family)

License: Proprietary non-OpenSource, Sourcecode licenseable

Reference applications
  • Safety relevant IoT applications (netpp on FPGA)
  • Multi channel WS2812B LED strip control through PWMPlus IP core
  • TFT/LCD display interfacing
Documentation

 

cordula

No longer maintained. All ‘cordula’ development is merged into the new ‘dombert’ SoC configuration.

dorothea

The dorothea SoC (based on the legacy PyPS core) is superseded by the alpha development stage dombert SoC using the ZPUng v1.1 architecture. It is meant to be the full drop-in replacement for the dorothea MJPEG/h264 accelerator and streaming engine (see dombert SoC below)

cranach

The next generation for ‘high speed’ netpp on FPGA with built in Tri speed Ethernet MAC. The entire system can also be run as virtual SoC (in-the-loop simulation).

  • ZPUng v1.1
  • RGMII and GMII interface,
  • Configureable DMA and Scratchpad memory for fast transfers
  • PWMPlus and standard interfaces IP (SPI, UART, ..)
  • Family support for Spartan6, ECP3, ECP5

Reference applications: netpp IoT stack with UDP/IP, ARP and ICMP support, RS485 I/O, Realtime PWM.

Documentation

dombert

The dombert SoC is considered a ZPUng based backport of the no longer maintained PyPS ‘dorothea’ SoC. It requires approx. half of the logic elements and runs at a higher speed, although the ZPUng execution speed is slower. We are currently in process of verifying all previous functionality. Working (alpha):

  • MJPEG streaming
  • DMAA engine
  • 100M Ethernet stress test passed

Not yet working:

  • GigE UDP engine
  • FLiX compression/entropy coding (h264 accelerator)
  • FX2 FIFO interface