IP cores

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Für spezifische Zwecke setzen wir gerne FPGAs ein:

  • Schnelle synchrone Bild-Vorverarbeitung, Videokompression
  • Spezielle DSP-Anwendungen, Rechenbeschleuniger
  • Komplett anpassbare SoC-Designs (embedded Videoprocessing)
  • Reliable Computing / Safety (verifizierbare State machines)

IP-Core Übersicht:

  • cCAP: konfigurierbare Applikationsprozessoren
  • Cottonpicken Engine: DSP-Beschleuniger-Pipeline für Video-Applikationen (Debayer, Filterkernels, Matrizen)
  • JPEG Encoder:
    • L1: ‘one lane multiplexed’ Pipeline für YUV420 Video
    • L2: ‘two lane simultaneous’ Pipeline für YUV422 oder multi channel monochrome Anwendungen

cCAP: massgeschneiderte Applikationsprozessoren

Eigene Prozessoren entwickeln? Ein Ding der Unmöglichkeit?

Wir haben es trotzdem getan. Die nach einigen Anläufen 2014 neuentwickelte ZPUng-Architektur zeichnet sich durch Kompabilität zur bestehenden ZPU (mit Debugger, GCC-Support, usw.) aus und kann mit der bestehenden Toolchain verwendet werden. Die ZPUng-Architektur ist dank ihrer höchst einfachen Opcode-Struktur vollständig verifizierbar. Korrekte Funktion von Programmcode ist somit beweisbar und kann mit realen Anwendungsszenarien in die Simulation gesteckt werden. Dazu haben wir eigene Co-Simulations-Erweiterungen entwickelt.

Die 32-Bit ZPU-Architektur hat sich im Vergleich zu klassischen CPU-Ansätzen (Microblaze, lm32, avr) als äusserst kompakt erwiesen: Ein komplettes Bare-Metal-System mit UDP/IP-Networking passt in ca. 12kB RAM, der CPU-Kern benötigt in der ‘minimalen’ Konfiguration ca. 800-900 LUT-Elemente auf dem FPGA. Grössere Programmodule können via SCACHE-Erweiterung auf externe SPI-Flashes ausgelagert werden (‘XIP’: execute in place).

Momentan sind folgende System-On-Chip Referenzdesigns auf Anfrage verfügbar:

  • agathe: OpenSource-SoC mit Zealot CPU: Einfache Soft-CPU für FPGAs für Konfigurationsaufgaben
  • beatrix: SoC mit ZPUng core: Schnelle Soft-CPU mit Beschleuniger-Optionen
  • cranach/dagobert: IoT-Lösung für kleine/grössere FPGAs (netpp-on-FPGA)
  • dombert: MJPEG streaming und Netzwerk-SoC für hochperformante Ethernet-Übertragung

 

IP cores

Overview:

  • Cottonpicken Engine
  • JPEG Encoder IP
  • cCAP: customizeable application processors and System on Chip solutions for networking and video processing

Cottonpicken Engine

The Cottonpicken Engine is an in-house micro coded engine that has the following functionality:

  • Bayer pattern decoding into various formats (YUV 4:2:2, YUV 4:2:0, RGB, programmable delays)
  • 3×3, 5×5 filter kernels
  • Specific matrix operations, cascadeable

It is capable of running at full data clock (pixel clock) up to 150 MHz, typically (platform dependent).

The engine is only available as a closed source netlist object as part of a development package.

JPEG Encoder IP

We have developed our own, machine vision proof JPEG encoder which is available for third parties with partial source code licensing options (VHDL only). The supported pixel bit depth is up to 12 bits. For JPEG header generation, a SoC and DMA engine is typically required. The JPEG IP is available in two variants:

  • L1 monochrome multiplexed pipeline (150 MHz pixel clock on Spartan6)
  • L2 dual pipe simultaneous encoding for high quality YUV422, for example 1280×720@60fps (up to 100 MHz pixel clock)

Board supply packages for eval kits:

  • Spartan6 Gigabee module from Trenz electronic
  • Versa ECP5 development kit
  • HDR60 from Lattice semiconductor (license required)

Also, we can provide a simulator package as Linux Container or virtual machine. It can be used to test the virtualized encoder HDL with existing PNG images, see [ Link ]. This is a full bit accurate model to prove compliance to existing reference software algorithms.

Further resources on request:

cCAP SoC Reference designs

These System on Chip designs consist of a fully configureable CPU plus standard peripherals and can be customized with special interfaces. The CPU can be programmed with GCC and is accessed via ICE JTAG during development.

[ more … ]

 

The MaSoCist build system

The pun is intended: Applying a linux kernel configuration approach onto a hardware system turned out to be painful. However, it turned to pay off in the following scenarios:

  • Cross platform: Simulate and synthesize reusable code for various architectures (Lattice ECP series, Xilinx Spartan series, …)
  • Configure peripheral interface instances
  • Automated generation of address decoders, peripheral instances and memory map from gensoc – our in house SoC generator.
  • Optional translation from IP-XACT, automated design rule check
  • Generate hardware configuration, software drivers and corresponding register documentation in one ‘call’. For example, all our reference documentation is automatically in sync with the register HDL.

It allows vendor specific designs and extensions without the need to OpenSource, therefore it is available in two license variants:

The MaSoCist opensource v0.10 release is available for free as standalone Linux based Docker container, including:

  • GHDL simulator and ghdlex co-simulation extensions
  • VirtualChip setup, virtual UART, FIFO, etc. for communication with real software for regression tests
  • Limitations: Spartan6 RAM models missing, hardware/vendor specific HDL libraries not included, no XML to HDL possible.

Simulation models

Full simulation models are available for all our IP cores that can be co-simulated with custom IP or run ‘live’:

See also VirtualChip page.