For quite a while I wouldn’t have said, it’s impossible, but wouldn’t put much effort in it either. Why, if you have a spare $1 microprocessor that can run a simple netpp communication stack just fine.
Well, sometimes it’s time to try something else: Running a soft core CPU (ZPU) on small FPGAs has found some interest, due to the limited resource consumption, but full freedom when it comes to specific interfaces, such as
- Programmable PWM engines (motor control)
- Many RS485 capable interfaces (that classic uCs don’t have)
- Safety proof specific state machines
The ZPU will even fit on a $5 FPGA and still leave enough space for the specific interfaces. It is a slow stack machine, even the fastest pipelined implementations don’t really beat the MIPS alike architectures, however this doesn’t bother us when we just have to configure a set of registers, moreover, the ZPU architecture compensates with quite some code density.
Also, for an update, we have implemented a faster, pipelined and configureable version of a stack machine with ZPU compatible front end, called ZPUng.
To keep a long sermon short: A full netpp stack running over a UART interface fits in less than 15kB of memory. And runs on a MachXO2-7000 from Lattice, for example, with less than 50% logic usage.
Who’s still saying that an FPGA is too dumb for the internet?
Ok, there’s one little missing piece: The TCP/IP stack and the ethernet MAC. It may make sense to separate core and communication section for safety reasons and use:
- esp8266 WLAN chip (not for industrial)
- Wiznet 5100/5300 TCP-on-chip
This solution was presented on the Embedded World Conference 2016 in Nuremberg. The published documentation can be downloaded for free in the web shop.